With the increase in complexity of modem integrated circuitry, the need to mathematically model the circuitry prior to fabrication has become more important. While the modeling of digital circuitry as well as analog circuitry has been performed for many years using computer analysis, modeling has recently become more important because of the size and complexity in modem integrated circuitry. Many modeling tools currently exist that may be used to check or verify the validity of a circuit prior to its construction. Some of these tools model the digital circuit at the register transfer level (RTL) of the digital circuit while other tools model the digital circuits at the gate level.
A typical design process wherein an integrated circuit is taken from conception to construction includes a variety of steps. In a first step, the conceptual nature of the integrated circuit is determined. The conceptual nature typically relates to the overall desired functions of the digital circuit. In the case of a complex microprocessor, the conceptual nature of the circuit is typically modeled in a high level language and verified using a high level simulator. Various tools exist to model the complex logic functions implemented in the circuit to ensure that all desired logic functions will be performed.
Once the conceptual nature of the circuit is determined, the RTL level model of the digital circuit is designed based upon the conceptual model and is modeled on a digital computer using an RTL modeling tool. At this time, the design of the circuit, as modeled within the RTL modeling tool, may be used to verify the design. Further, the RTL modeling tool, in some cases, may allow the validity of the circuit as modeled to be cross referenced to the high level language model. The RTL level model may also be used to alter the design of the circuit within the RTL level modeling tool.
Once the RTL level model is completed, it is then transformed into a gate level model wherein individual logic gates required to perform the logic functions of the circuit as modeled in the RTL level model are implemented. Further verification, testing, and optimization testing may be performed using gate level model tools in conjunction with the gate level model. Because the gate level model implements actual logic functions using logic gate models while the RTL level model consists primarily of logical instructions, the function of the gate level model must be verified with respect to the RTL level model. Various tools exist to verify the operation of the gate level model with respect to the RTL level model.
Once the gate level model is completed, the gate level model is transformed into a transistor or switch level model. The switch level model is then used to create the physical design for the integrated circuitry and the physical design is used to generate the mask sets which are employed in the manufacturing process to create the actual integrated circuit. The mask sets are then used in the fabrication processes to depose the circuit on a semiconductor wafer or other substrate.
Because modem integrated circuitry is extremely complex and the number of gates implementing a particular circuit may include millions of transistors, it is important to verify the operation of the integrated circuitry at each level prior to its construction. Thus, various programs have been developed at the RTL level and at the gate level to simulate the operation of the integrated circuit design. However, it has been determined that a simple simulation of the integrated circuit model is insufficient to ensure the correct operation of the integrated circuitry. As one skilled in the art will readily appreciate, with the number of transistors in a large integrated circuit exceeding one million transistors, not all possible cases may be simulated so that the simulation results may be verified. Even if the complete number of cases could be simulated, as one skilled in the art will readily appreciate, the number of variations typically exceeds the capability of a tool to check the cases.
Because it is relatively easier to verify the operation of an integrated circuit model at the RTL level than either at the gate or switch level model, designers often rely on the validity of the RTL level model as a benchmark. However, even though the RTL level model may be judged correct by a designer, the gate level model and switch level model may have developed errors in their operation through the transformation from the RTL level model. Thus, it is desirable to ensure that both the transistor level model and the gate level model operate in accordance with the RTL level model.
Further, logic is often optimized within the gate level model to reduce the area required to construct the circuit, to increase the speed of operation of the circuit, to reduce the power consumption of the circuit, or to optimize the logic operation of the circuit itself. Once the gate level logic of the circuit model has been optimized, its operation must be verified with respect to the RTL level model or the prior gate level model.
In some situations it is advantageous in order to benefit from newer fabrication technologies to take an existing integrated circuit design and to convert the design to take advantage of the new process technology. In this situation, a gate level model is extracted from a prior switch level model and then mapped to a new gate level library implementing the new fabrication process. Once the new gate level model has been generated, the logical operation of the new gate level model must be verified with respect to the prior gate level model or the prior RTL level model.
In some situations, a scan logic circuit is inserted into a circuit model after the model has been created. While the scan logic circuit is generally intended not to affect the normal operation of the integrated circuitry, the addition of the scan logic circuit, if inadvertently placed, may affect the logic operation of the integrated circuit. Thus, the circuit model including the scan logic circuit must be checked to determine whether the normal operation of the circuit has been affected, and checked against the prior gate level model or RTL level model.
FIG. 1 shows a logical representation of a first circuit model 540 and a second circuit model 542. As is known in the art, a circuit model includes a plurality of inputs 502 and a plurality of outputs 504 with certain logical functions required for the outputs depending upon the set of inputs. Within the first circuit model 540, or any circuit model, are also a plurality of storage elements 506, 508, 510, 512. In an actual circuit at power-up, storage elements have unknown values unless forced to specific known states. Thus, in a typical integrated circuit, a set of input instructions sets the storage elements to known values.
As is diagrammatically shown in FIG. 1, the first circuit model includes a plurality of storage elements. Each of these storage elements typically receives input data from a number of sources. The sources providing data to storage elements include inputs, stored values of other storage elements, and stored value of the storage element itself. Input values are provided to a storage element through a "cone" of logic as represented by elements 514, 516, 518, and 520. The cone of logic is diagrammatically illustrated as a triangle. The cone of logic may include any number and variety of logical functions with the output of the cone of logic providing an input value to the storage element.
FIG. 1 also illustrates a second circuit model that is related to the first circuit model in some manner. In some situations, such as those described above, the first circuit model and the second circuit model are compared to verify the equivalence of operation of the circuit models. In this situation the inputs of the first circuit model and the inputs of the second circuit model correspond to one another while the outputs of the first circuit model and the outputs of the second circuit model also correspond.
Prior verification tools looked simply at the inputs and outputs of the respective circuit models to determine whether the functions of the circuits were equivalent. However, as was previously discussed, a simulation of this type cannot thoroughly check the operation of the circuits. Such is the case because the values of the storage elements within the respective circuit models must be compared as well to ensure an equivalence between the circuit models. In many situations it is desirable to verify an exact equivalence between a first circuit model and a second circuit model. Such an equivalence operation may only be determined by viewing the storage element contents at each operation step of the models.
Certain commercially available circuit modeling tools have functions built in to relate storage element contents of storage elements of one circuit model to storage elements of a second circuit model in order to verify the operation of the circuits. However, the correspondences between the storage elements of the respective models must be provided by the user of the tool. Thus, even though these tools may verify the logical functions of the respective storage elements of the first circuit model and the second circuit model, the relationship or correspondence of the respective storage elements must be provided. These tools do not, by themselves, determine the correspondence between the storage elements of the respective models. Thus, prior techniques have been developed in an attempt to match storage elements of a first circuit model with storage elements of a second circuit model.
One particular prior solution took a simplified step in matching storage elements of a first circuit model with storage elements of a second circuit model. The solution compared the names of storage elements of a first circuit model with storage elements of a second circuit model in order to determine correspondences. As one skilled in the art will readily appreciate, however, there is little basis for matching storage elements based upon the names assigned to particular storage elements. If the first circuit model and the second circuit model are generated from different circuit hierarchies, there will be no match of names between the circuit models. Thus, the prior solution simply identifying names between one circuit model and another circuit model is insufficient at best.
Thus there exists a need in the art for a method and apparatus for determining the correspondences between storage elements of a first circuit model and storage elements of a second circuit model.